Innopower's memory compilers provide designers with a variety of embedded memory in the form of reusable IP that facilitate ASIC and SoC designs.

All Innopower memory compilers are developed using custom memory design techniques following a dedicated streamline process to achieve industry-leading results in die size, speed, and power. All Faraday's memory compilers are configured using EDA tools, BIST codes, and parameterized by power ports, making them ideal for highly integrated chip applications.

Being a strategic partner of foundries, Innopower memory compilers are configured to the logic process, high-voltage process, mix-mode process, and other special processes (Such as the CIS-CMOS Image Sensor process). The figure below illustrates the full-range of the memory IPs, which covers the advance process technologies from 0.35 µm to 55 nm.

Delivery Package

There are two types of packages to deliver to our customers. One is the Design Kit and the other is the Tape-out Kit. Users are welcomed to download our database for evaluation. Please register through our web based, e-Service system.

Deliverables

By selecting our memory compilers, designers are assured of a perfect match with their targeted applications. Each compiler is delivered at an exact configuration with the following deliverables:

• Verilog timing/simulation model
• VHDL timing/simulation model
• Synopsys Static Timing Model
• Spice-level netlist for LVS
• GDSII layout database
• P&R model
• Schematic symbols
• Data sheet/application note
• BIST RTL code support

For more details on Innopower's memory IPs, you may link to Innopower web site to view the relevant sheets and documents to simplify your evaluation process.