This Ethernet solutions include digital 10/100/1000 Ethernet MAC and 10/100 Ethernet PHY for
0.18 µm, 0.13 µm, 90 nm and 65 nm processes. With thorough considerations for easy integration,
reusability, scalability, and interoperability, this silicon-proven Ethernet PHY and MAC cater to the
increasing SoC integration demands to develop a wide range of Ethernet-enabled devices with less effort and
shorter lead time.
Ethernet 10/100/1000 MAC IP
Ethernet 10/100/1000 MAC (FTGMAC100_S) is an Ethernet controller with DMA functions.
This IP includes AHB wrapper for easy integration, DMA engine, on-chip memories (Tx and Rx FIFO), MAC,
and MII/ GMII/ RMII interface, which are also part of the functional blocks. FTGMAC100_S provides AHB master
capability and is fully compliant with IEEE 802.3 specification for 10/100 Mbps, and IEEE 802.3z for 1,000 Mbps
Ethernet specifications. With a DMA engine, this controller can maximize the system performance by reducing
the CPU loading while minimizing the FIFO size.
In order to reduce the processing load of the host CPU, FTGMAC100_S implements TCP, UDP, and the IP header checksum generations and validations, and supports the VLAN tagging. For the QoS and CoS requirements, FTGMAC100_S supports high priority queues to reduce the processing load of the host CPU for transmitting packets.
- Equipped with AHB bus interface to support bus master and slave mode
- Equipped with DMA engine for transmitting and receiving packets
- Supports TCP, UDP, IP header checksum offloads
- Supports IEEE 802.1Q VLAN tag insertion and removal
- Supports High Priority Transmit Queue for QoS and CoS applications
- Supports Wake-on-LAN function with three wake-up events: Link status change, Magic packet, and Wake-up frame
- Independent TX/RX FIFO
- Supports half-duplex and full-duplex (Full-duplex operation supported only in 1000 Mbps mode)
- Supports flow control for full duplex and backpressure for half duplex
- Supports MII/GMII/RMII interface
- Supports Jumbo packets (9K bytes)
Ethernet 10/100 PHY IP
10/100 Base-TX (Twisted-pair cable) fast Ethernet DSP-based PHY. Being fully compliant with the
10/100 Base-TX Ethernet standards (IEEE 802.3/802.3u and ANSI X3.263-1995 (FDDI-TP-PMD)), the 10/100 Ethernet PHY
are mass production proven in several foundry processes, including 0.18 µm, 0.13 µm, 90 nm, and 65 nm.
- Fully compliant with 100 Base-TX and 10 Base-T PMD level standards - IEEE802.3/802.3u and ANSI X3.263-1995 (FDDI-TP-PMD)
- DSP based adaptive line equalizer for superior immunity to noise and inter-symbol interference
- DSP controlled symbol timing recovery circuit
- Supports MII interface to link layer
- Supports serial and parallel management control interface
- Multi-function LED drivers for Link, Collision, Duplex, Rx and Tx
- Supports full-duplex and half-duplex modes
- Provides three power-down mode
- Supports Auto-MDIX feature