Synchronous Ultra-High Speed Single-Port-SRAM (UHS-SRAM): SE Type

In addition, Innopower provides the synchronous ultra-high speed Single-Port-SRAM (UHS-SRAM): The SE-type compiler, for certain processes. UHS-SRAM can be incorporated with the Innopower standard cell library. Different combinations of words, bits, and aspect ratios can be used to generate the most desirable configurations. UHS-SRAM is designed for the ultra-high-speed applications, such as the CPU, DSP, and real-time multimedia applications.

Given the desired size and timing constraints, the Innopower memory compiler is capable of providing the suitable synchronous SRAM layout instances within minutes. It automatically generates the data sheets, Verilog/VHDL behavioral simulation models, P & R (place-and-rout) models, and the test patterns to be used in the ASIC designs. The length of duty cycle can be neglected as long as the setup/hold times and minimum high/low pulse widths are satisfied. This provides a more flexible CK falling edge during each operation. Both the word write and the byte write operations are supported.

Features

• Supports synchronous read and write operations
• Zero DC current except the process leakages
• Low AC power
• One read/write port
• Fully-customized layout density
• Supports automatic power-down mechanism to eliminate DC current
• Clocked address inputs and CSB to RAM at the CK rising edge
• Clocked WEB input to RAM at the CK rising edge
• Clocked DI inputs to RAM at the CK rising edge
• Supports byte write and word write operations
• Selective aspect ratios to best-fit chip floor plan
• Includes Verilog/VHDL timing/simulation model generators
• Includes SPICE netlist generator
• Includes GDSII layout generator
• Supports BIST code