The miniLib™ is an ultra high density standard cell library family optimized for low-cost and lower-power applications. The high density originates from the proprietary compact cell architecture and elaborate circuit topologies. The miniatured geometry of devices also contributes to significant reduction in dynamic and leakage power consumption. As far as routability is concerned, each miniLib™ cell is optimized for the up-to-date APR (Automatic Place-and-Route) routers and verified by rigid pin accessibility validation flow. With the perfect routability, miniLib™ provides low-cost and low-power features to the competitive chips with accelerated design time in SoC implementation.

Features

• Rich set of cell functions for logic optimization
• Abundant driving strengths for timing closure
• Plenty of functional cells with balanced delay for clock tree design
• Corresponding scan and non-scan flip-flops
• All pins are located on routing grids
• Only transistor gates are driven by input pins for all cells
• Highly optimized for area, dynamic and leakage power
• Routability is ensured by elaborated pin accessbility

Library Benchmark- miniLib in Area & Power

With one practical IP, a 120K gate-count PCIX, miniLib shows the advantage over the competitor in area and power under different timing constraints.

Area of PICX (120K Gates)

Dynamic Power of PCIX (120K Gates)

Leakage Power of PCIX (120K Gates)

Library Benchmark- miniLib in Route-ability

In the 110K gate count Switch with complex connectivity, miniLib gains 16% area reduction compared to its competitor. The excellent area saving is due to miniLib's compact cell architecure in conjuction with the thoughtful pin-out location and routing track consideration.