Overview

This Serial ATA (SATA) solution includes a device controller (FTSATA110), a host controller (FTSATA100) and transceiver PHYs in various foundry processes. Both controllers come with fully synthesizable RTL codes. The solution is a high-performance compact modular design with competitive leading-edge attributes.

FTSATA100 is a Serial ATA (SATA) host controller which is fully compliant with the SATA 1.0a/II and the Advanced Host Controller Interface (AHCI) specifications. The host controller supports 1.5 and 3.0 Gbps data transfer rates. Without the software intervention, the host controller can deal with the command list data structure to offload the CPU and automatically transmit and receive data on the SATA bus. The system bus provides a PVCI or 32-bit AHB bus interface.

Serial ATA PHY

FTSATA110 is a Serial ATA (SATA) device controller with the Link and Transport digital logic. The data bus width between PHYs is selectable (through external pins) as 20-or 40-bit. The system bus also provides a PVCI or 32-bit AHB bus interface. Serial ATA PHY The SATA PHY supports both host and device on the SATA Link Layer with automatic 1.5 and 3.0 Gbps speed negotiation. The built-in low-jitter PLL guarantees very low bit error rate. The integrated Built-In-Self-Test (BIST) mode and the loopback function eliminate the need for high speed test equipments. It provides a low speed interface to interact with the Link Layer by a 40-bit data bus. The PHY is available in various foundry processes.

Highlights

• Compliant with SATA-II specification
• Integrated BIST
• Supports K28.5 comma detection
• OOB signal detection and transmission
• Signal clock to link layer: 75MHz at 3.0G and 37.5MHz at 1.5G
• Slumber, partial power mode support
• Fully partitioned layered structure
• Configurable FIFO width in transport layer
• Application layer complies with ATA/ ATAPI standards