This LVDS, mini-LVDS and RSDS™ IPs are mass production proven high Speed I/O Interfaces for display and chip-to-chip interconnections. Our LVDS family platform is a CMOS differential line transmitter and receiver designed for applications that require ultra low power dissipation and high data rate. These IPs are available with process technologies ranging from 55nm to 0.35µm and a data rate of up to 945 Mbps utilizing low voltage differential signaling technology. The Reduced Swing Differential Signaling (RSDS™) is a signaling standard that defines the chip-to-chip interface output characteristics, which act as a protocol between the flat panel timing controllers and the column drivers. The mini-LVDS is a signaling standard acting as a protocol between the flat panel timing controllers and the column driver. Key features of the IPs are listed below.

LVDS Receiver Features

• Support 20 to 135MHz shift clock
• 4:28 / 5:35 data channel expansion at a data rate of up to 945MHz
• Support VGA, SVGA, XGA and single pixel SXGA
• Rising and falling edge clock triggered outputs
• Support power-down mode
• Compliant with TIA/EIA-644 LVDS standard

• Support 20 to 85MHz shift clock
• 4:28 data channel compression at a data rate of up to 595MHz per channel
• Support VGA, SVGA, XGA and single pixel SXGA
• Rising and falling edge clock triggered outputs
• Support power-down mode
• Compliant with TIA/EIA-644 LVDS standard

• Input data clock rate between 22.5 to 61.5MHz
• Mini-LVDS clock frequency rage: 81 ~ 202.5MHz
• Support mini-LVDS channels: 3, 4, 5, or 6 pairs
• Support RGB data bit: 6 or 8 bits
• Low Electro Magnetic Interference (EMI)

• Support a signal rate of up to 200 Mbps
• Differential signal swing of 200 mV with 100Ω load
• Low power design
• Embedded skew control function
• Low Electro Magnetic Interference (EMI)