FA726

FA726TE is a generic 32-bit RISC processor with the highest performance/cost with supreme power-saving efficiency among the CPU solutions in the market. FA726TE is designed with the super-scalar micro-architecture and advanced load/store unit which consists of a synthesizable CPU core, an MMU, separate caches, and scratchpads. The CPU core operates of up to 1.8 DMIPS/MHz and implements the ARM V5TE® ISA based on the innovative dual-issue, in-order execution, and 13-stage pipeline with the advanced dynamic prediction, static prediction, and return stack apparatus. Its configurable features include the cache sizes, scratchpad sizes, floating point unit, optional L2 cache, and an optional AXI/AHB bus interface.

To meet the complex processing of the leading-edge applications, high-performance and power-saving CPU cores are becoming a de facto requirement for a system. FA726TE delivers the high performance of up to 2160 Dhrystone MIPS for the intensive computing of the application software and middleware, and consumes lower than 250mW as a power optimized configuration. Targeted the applications of the set-top box, IP TV, network, SAN/NAS, netbook, digital entertainment devices, MFP, navigation, and multi-format wireless gateway, FA726TE at 65 nm and 55 nm running at 1.2 GHz is available now.

FA726TE supports the standard ARM tool chains, such as the ARM ADS, RVDS, and GNU tool chains. The ICE logic serves as the debugging interface and communicates with external ICE hardware through the ARM compliant JTAG style ICE interface. In addition, Faraday provides the development platform named SoCreative!™ with all the drivers based on WinCE6.0 and Linux2.6. It is a modularized platform enabling easy integration for an system verification.

Key Features

• ARM v5TE® instruction set
• 13-stage pipeline superscalar
• Ultra-high frequency running at 1.2 GHz under the worst-case conditions in the UMC logic
• 65 nm/55 nm SP/RVT processes
• 1.8 DMIPS/MHz performance
• Highly accurate mechanism of branch prediction constructed by dynamic prediction, static prediction, and return stack apparatus
• Support vector floating point unit
• Support ARM CoreSight PTM-A9
• Two-level interrupt priority

• Provide Instruction and data caches
• Support of up to six outstanding on-blocking data caches
• Cache lockdown function
• Instruction and data scratchpads with DMA function
• Support write buffer

• Enhanced ARMv5® compliant MMU
• Fully-associative 8-entry ITLB
• Fully-associative 8-entry DTLB
• 64-entry 4-way Unified TLB
• Hardware table walk

• Support Bi-endian
• Power-saving control unit
• Support standard ARM®ICE interface
• Support standard ARM tool chain
• Configurable 64-bit/128-bit AXI bus or 32-bit/64-bit AHB bus
• Optional L2 cache