FA626TE

The FA626TE is a 32-bit RISC processor with excellent computing and power efficient capability. The powerful processor is an ARMv5TE ISA compliant CPU core which employs four AHB or AXI interfaces with configurable 32-bit/64-bit width to communicate with external memory and devices. The ARMv5TE instruction set has many advantages to benefit our customers: The Thumb® instruction set assists in reducing the code size, especially in the use of the embedded ROM/flash; the DSP instructions are accommodating to the media and other signal processing acceleration. Operating at frequency of up to 533 MHz at 0.13 µm process and 800 MHz at 90 nm process, respectively, under the worst-case conditions, FA626TE is a high performance CPU core to serve the applications requiring the high performance embedded CPU core.

FA626TE supports the standard ARM tool chains, such as the ARM ADS, RVDS, and GNU tool chains. The ICE logic serves as the debugging interface and communicates with external ICE hardware through the ARM compliant JTAG style ICE interface. In addition, Faraday provides the development platform named SoCreative!II TM with all the drivers based on WinCE6.0 and Linux2.6. The development board is a modularized platform enabling new design to be plugged in for an easy system verification.

FA626TE Key Features

• ARMv5TE® instruction set
• 8-stage pipeline
• Branch prediction- Static and 2-bit counter
• Single phase clock
• Memory-mapped I/O
• 32 x 32 MAC

• Instruction and data caches
• Non-blocking data cache access
• Cache lockdown
• Instruction and data scratchpads
• Write buffer

• Enhanced ARMv5® compliant MMU
• 8-entry fully-associative ITLB
• 8-entry fully-associative DTLB
• 64-entry 2-way set associative Unified TLB
• Hardware page-walking

• AMBA® 2.0 bus interface (AHB) for an easy SoC integration
• Support Bi-endian
• Dual power-saving modes
• Support standard ARM®ICE interface
• Support standard ARM tool chain
• Support ASIE external coprocessor

FA606TE

FA606TE is an ultra-low power 32-bit RISC with the synthesizable and configurable features. With the equivalent 40-K synthesized gate, this tiny ultra-low power CPU core is specially designed for those applications that are both power sensitive and cost sensitive, such as the general micro controller, SSD controller, industrial controller, bridge controller, and portable audio/video processor. In the 32-bit tiny core market, FA606TE is one of a few cores with the built-in DSP extensions that enhance the DSP computing capabilities. Moreover, the 5-stage pipeline provides more considerable clock performance than other CPU cores. The configurable features of FA606TE include the optional Memory Protection Unit (MPU), Local Bus Controller (LBC), Instruction Memory (I-RAM) and Data Memory (D-RAM) from 0 KB to 8 MB, respectively. These distinguish features enable users to customize the their FA606 CPU cores for either in the area driven or in the performance optimization or even in both.

With the sophisticating tendency of the application and software, 8-bit and 16-bit MCUs are no longer affordable in the demanded performance in the embedded SoC world. The micro processor is often expected to be a control unit, handling the algorithms, simultaneously, running a simple Operation System (OS) built in some application software. Due to the requiring voice to replace the 32-bit RISC with the MCU in the high-end 8-bit/16-bit market from the customers, the synthesizable and customizable FA606TE is thus designed to maintain the equivalently competitive cost and power as the 8-bit/16-bit MCU with higher performance.

FA606TE supports the standard ARM tool chains, such as the ARM ADS, RVDS, and GNU tool chains. The ICE logic serves as the debugging interface and communicates with external ICE hardware through the ARM compliant JTAG style ICE interface. In addition, Faraday provides the development platform named i606 TM which is a modularized platform enabling the new design to be plugged in for an easy system verification.

FA606TE Key Features

• ARMv5TE® instruction set
• 5-stage pipeline
• Two-level interrupt priority
• Address space : 4 GB
• Single phase clock
• Memory-mapped I/O
• On-chip multiplier

• Separated instruction and data memory access
• Support memory-wait cycle
• Support bus slave function to access internal instruction and data memory
• AMBA 2.0 interface

• Area, power, and performance at the 0.13 µm process: 0.3 mm², 0.06 mW/MHz, and 180 MHz
• Support Bi-endian
• Power saving control unit
• Support standard ARM®ICE interface
• Support eCOS2.0 operating system