Low power consumption is critical to SoC designs, particularly for the growing number of portable applications. Longer battery life and use of cheaper package drive SoC designers constantly searching for “Cool” or “Green” IPs.

Innopower's low power IP portfolio, called Emerald Suite, includes IO, memory compilers and miniLib+™ Cell Libraries, work comfortably under 0.9V for 65, 55 and 40LP processes. Emerald Suite also comes with low leakage current and low clock tree loading. Innopower also provides low-power interface PHY such as USB2.0, USB3.0, mDDR, mDDR2, DDR2, DDR3, SATA 1.5/3/6G, PCI-Express 2.5/5G, 10/100 Ethernet. All these PHY are mass production proven and industry-standard certified. By working closely with foundries, Innopower provides “Cool” IP’s customized for specific processes, making the low power design feasible in many manufacturing facilities.

“Customers can seamlessly develop their designs with our low-power IP’s to create a complete solution and achieve maximum power efficiency,” said Raymond Leung, Chief Technology Officer at Innopower. “Developing competitive low-power solutions is our long-term technical commitment to help customers differentiate their products in their respective markets.“

Innopower’s miniLib+™ Cell Library
Innopower’s miniLib+™ cell library uses a series of new architectures that significantly reduce the power and area of chip design. Compared to other high density libraries, the miniLib+™ can help to reduce the power consumption by about 20% to 50%. It can also achieve about 10% to 20% in area reduction for the same design. Innopower's miniLib+™ is now available in many foundry processes.

 

Innopower’s Low-Power Memory Compiler (Power Gating):
Innopower's synchronous Low Power Memory compiler is optimized for very-low power designs. It is designed with power gating feature which offers three extra power saving modes, standby, retention, and sleep mode. Compared to the generic-type 32K x 8 SRAM simulated in 55 nm SP process, Innopower's low power memory compiler (power-gating) can save an average of about 70% and 96% power in retention mode and sleep mode separately. The timing definition and control signals of this power-gating memory compiler are simple and easy to use.

 

 
Fig-1 The power consumption of a 32K x8 SRAM in power saving mode

 

Fig-2 The power consumption of a 1K x4 SRAM in power saving mode

 

 

Low power Ethernet PHY IP

Low power Ethernet PHY IP, FXEDP118HP0A, is fully compliant with 100 Base-TX, 10 Base-T PMD level standards (IEEE 802.3u, FDDI-TP-PMD and 802.3). It is also compliant with 100Base-FX IEEE802.3u. This low power, high integrated Ethernet PHY IP is implemented in 0.162um MMC process. It offers superior feature of power management mode for Ethernet applications. Three power saving modes (PS1/2/3) are provides to save significant power when the Ethernet cable is not connected. The power consumption in 100 Base-TX mode and 10 Base-TX mode are 300mW and 350mW separately. FXEDP118HP0A is in mass production now.

 

 

Fig-3 The power consumption of FXEDP118HP0A PHY IP